/******************************************************************************
 ** File Name:      pinmap.h                                                  *
 ** Author:         Richard.Yang                                              *
 ** DATE:           03/08/2004                                                *
 ** Copyright:      2004 Spreatrum, Incoporated. All Rights Reserved.         *
 ** Description:    This file defines the structure of pin map.               *
 ******************************************************************************

 ******************************************************************************
 **                        Edit History                                       *
 ** ------------------------------------------------------------------------- *
 ** DATE           NAME             DESCRIPTION                               *
 ** 03/08/2004     Richard.Yang     Create.                                   *
 ******************************************************************************/

#ifndef _PINMAP_H_
#define _PINMAP_H_

#include "sci_types.h"
#include "sprd_reg.h"
#include "adi.h"

typedef struct {
	uint32_t reg;
	uint32_t val;
} pinmap_t;
int pin_init(void);
//int pin_init(pinmap_t * pinmap);

#define CTL_PIN_BASE			(SPRD_PIN_PHYS)

/* registers definitions for controller CTL_PIN */
#define REG_PIN_CTRL0                   ( 0x0000 )
#define REG_PIN_CTRL1                   ( 0x0004 )
#define REG_PIN_CTRL2                   ( 0x0008 )
#define REG_PIN_CTRL3                   ( 0x000c )
#define REG_PIN_CTRL4                   ( 0x0010 )
#define REG_PIN_CTRL5                   ( 0x0014 )
#define REG_PIN_RFSDA0                  ( 0x0020 )
#define REG_PIN_RFSCK0                  ( 0x0024 )
#define REG_PIN_RFSEN0                  ( 0x0028 )
#define REG_PIN_RFSDA1                  ( 0x002c )
#define REG_PIN_RFSCK1                  ( 0x0030 )
#define REG_PIN_RFSEN1                  ( 0x0034 )
#define REG_PIN_RFCTL15                 ( 0x0038 )
#define REG_PIN_RFCTL16                 ( 0x003c )
#define REG_PIN_RFCTL17                 ( 0x0040 )
#define REG_PIN_RFCTL18                 ( 0x0044 )
#define REG_PIN_RFCTL19                 ( 0x0048 )
#define REG_PIN_RFCTL20                 ( 0x004c )
#define REG_PIN_RFCTL21                 ( 0x0050 )
#define REG_PIN_RFCTL22                 ( 0x0054 )
#define REG_PIN_RFCTL23                 ( 0x0058 )
#define REG_PIN_RFCTL24                 ( 0x005c )
#define REG_PIN_RFCTL25                 ( 0x0060 )
#define REG_PIN_RFCTL26                 ( 0x0064 )
#define REG_PIN_RFCTL0                  ( 0x0068 )
#define REG_PIN_RFCTL1                  ( 0x006c )
#define REG_PIN_RFCTL2                  ( 0x0070 )
#define REG_PIN_RFCTL3                  ( 0x0074 )
#define REG_PIN_RFCTL4                  ( 0x0078 )
#define REG_PIN_RFCTL5                  ( 0x007c )
#define REG_PIN_RFCTL6                  ( 0x0080 )
#define REG_PIN_RFCTL7                  ( 0x0084 )
#define REG_PIN_RFCTL8                  ( 0x0088 )
#define REG_PIN_RFCTL9                  ( 0x008c )
#define REG_PIN_RFCTL10                 ( 0x0090 )
#define REG_PIN_RFCTL11                 ( 0x0094 )
#define REG_PIN_RFCTL12                 ( 0x0098 )
#define REG_PIN_RFCTL13                 ( 0x009c )
#define REG_PIN_RFCTL14                 ( 0x00a0 )
#define REG_PIN_RFCTL27                 ( 0x00a4 )
#define REG_PIN_XTL_EN                  ( 0x00a8 )
#define REG_PIN_RFFE_SCK0               ( 0x00ac )
#define REG_PIN_RFFE_SDA0               ( 0x00b0 )
#define REG_PIN_RFCTL28                 ( 0x00b4 )
#define REG_PIN_RFCTL29                 ( 0x00b8 )
#define REG_PIN_SIMCLK0                 ( 0x00bc )
#define REG_PIN_SIMDA0                  ( 0x00c0 )
#define REG_PIN_SIMRST0                 ( 0x00c4 )
#define REG_PIN_SIMCLK1                 ( 0x00c8 )
#define REG_PIN_SIMDA1                  ( 0x00cc )
#define REG_PIN_SIMRST1                 ( 0x00d0 )
#define REG_PIN_SIMCLK2                 ( 0x00d4 )
#define REG_PIN_SIMDA2                  ( 0x00d8 )
#define REG_PIN_SIMRST2                 ( 0x00dc )
#define REG_PIN_SD0_D3                  ( 0x00e0 )
#define REG_PIN_SD0_D2                  ( 0x00e4 )
#define REG_PIN_SD0_CMD                 ( 0x00e8 )
#define REG_PIN_SD0_D0                  ( 0x00ec )
#define REG_PIN_SD0_D1                  ( 0x00f0 )
#define REG_PIN_SD0_CLK0                ( 0x00f4 )
#define REG_PIN_SD1_CLK                 ( 0x00f8 )
#define REG_PIN_SD1_CMD                 ( 0x00fc )
#define REG_PIN_SD1_D0                  ( 0x0100 )
#define REG_PIN_SD1_D1                  ( 0x0104 )
#define REG_PIN_SD1_D2                  ( 0x0108 )
#define REG_PIN_SD1_D3                  ( 0x010c )
#define REG_PIN_IIS0DI                  ( 0x0110 )
#define REG_PIN_IIS0DO                  ( 0x0114 )
#define REG_PIN_IIS0CLK                 ( 0x0118 )
#define REG_PIN_IIS0LRCK                ( 0x011c )
#define REG_PIN_U0TXD                   ( 0x0120 )
#define REG_PIN_U0RXD                   ( 0x0124 )
#define REG_PIN_U0CTS                   ( 0x0128 )
#define REG_PIN_U0RTS                   ( 0x012c )
#define REG_PIN_PTEST                   ( 0x0130 )
#define REG_PIN_ANA_INT                 ( 0x0134 )
#define REG_PIN_EXT_RST_B               ( 0x0138 )
#define REG_PIN_CHIP_SLEEP              ( 0x013c )
#define REG_PIN_XTL_BUF_EN0             ( 0x0140 )
#define REG_PIN_XTL_BUF_EN1             ( 0x0144 )
#define REG_PIN_CLK_32K                 ( 0x0148 )
#define REG_PIN_AUD_SCLK                ( 0x014c )
#define REG_PIN_AUD_ADD0                ( 0x0150 )
#define REG_PIN_AUD_ADSYNC              ( 0x0154 )
#define REG_PIN_AUD_DAD1                ( 0x0158 )
#define REG_PIN_AUD_DAD0                ( 0x015C )
#define REG_PIN_AUD_DASYNC              ( 0x0160 )
#define REG_PIN_ADI_D                   ( 0x0164 )
#define REG_PIN_ADI_SYNC                ( 0x0168 )
#define REG_PIN_ADI_SCLK                ( 0x016c )
#define REG_PIN_LCM_RSTN                ( 0x0170 )
#define REG_PIN_DSI_TE                  ( 0x0174 )
#define REG_PIN_MTDO_ARM                ( 0x0178 )
#define REG_PIN_MTDI_ARM                ( 0x017c )
#define REG_PIN_MTCK_ARM                ( 0x0180 )
#define REG_PIN_MTMS_ARM                ( 0x0184 )
#define REG_PIN_MTRST_N_ARM             ( 0x0188 )
#define REG_PIN_DTDO_LTE                ( 0x018c )
#define REG_PIN_DTDI_LTE                ( 0x0190 )
#define REG_PIN_DTCK_LTE                ( 0x0194 )
#define REG_PIN_DTMS_LTE                ( 0x0198 )
#define REG_PIN_DRTCK_LTE               ( 0x019c )
#define REG_PIN_NFWPN                   ( 0x01a0 )
#define REG_PIN_NFRB                    ( 0x01a4 )
#define REG_PIN_NFCLE                   ( 0x01a8 )
#define REG_PIN_NFALE                   ( 0x01ac )
#define REG_PIN_NFREN                   ( 0x01b0 )
#define REG_PIN_NFD4                    ( 0x01b4 )
#define REG_PIN_NFD5                    ( 0x01b8 )
#define REG_PIN_NFD6                    ( 0x01bc )
#define REG_PIN_NFD7                    ( 0x01c0 )
#define REG_PIN_NFD10                   ( 0x01c4 )
#define REG_PIN_NFD11                   ( 0x01c8 )
#define REG_PIN_NFD14                   ( 0x01cc )
#define REG_PIN_NFCEN0                  ( 0x01d0 )
#define REG_PIN_NFWEN                   ( 0x01d4 )
#define REG_PIN_NFD0                    ( 0x01d8 )
#define REG_PIN_NFD1                    ( 0x01dc )
#define REG_PIN_NFD2                    ( 0x01e0 )
#define REG_PIN_NFD3                    ( 0x01e4 )
#define REG_PIN_NFD8                    ( 0x01e8 )
#define REG_PIN_NFD9                    ( 0x01ec )
#define REG_PIN_NFD12                   ( 0x01f0 )
#define REG_PIN_NFD13                   ( 0x01f4 )
#define REG_PIN_NFD15                   ( 0x01f8 )
#define REG_PIN_CCIRD0                  ( 0x01fc )
#define REG_PIN_CCIRD1                  ( 0x0200 )
#define REG_PIN_CMMCLK                  ( 0x0204 )
#define REG_PIN_CMPCLK                  ( 0x0208 )
#define REG_PIN_CMRST0                  ( 0x020C )
#define REG_PIN_CMRST1                  ( 0x0210 )
#define REG_PIN_CMPD0                   ( 0x0214 )
#define REG_PIN_CMPD1                   ( 0x0218 )
#define REG_PIN_SCL0                    ( 0x021c )
#define REG_PIN_SDA0                    ( 0x0220 )
#define REG_PIN_SPI2_CSN                ( 0x0224 )
#define REG_PIN_SPI2_DO                 ( 0x0228 )
#define REG_PIN_SPI2_DI                 ( 0x022c )
#define REG_PIN_SPI2_CLK                ( 0x0230 )
#define REG_PIN_SPI0_CSN                ( 0x0234 )
#define REG_PIN_SPI0_DO                 ( 0x0238 )
#define REG_PIN_SPI0_DI                 ( 0x023c )
#define REG_PIN_SPI0_CLK                ( 0x0240 )
#define REG_PIN_MEMS_MIC_CLK0           ( 0x0244 )
#define REG_PIN_MEMS_MIC_DATA0          ( 0x0248 )
#define REG_PIN_MEMS_MIC_CLK1           ( 0x024c )
#define REG_PIN_MEMS_MIC_DATA1          ( 0x0250 )
#define REG_PIN_KEYOUT0                 ( 0x0254 )
#define REG_PIN_KEYOUT1                 ( 0x0258 )
#define REG_PIN_KEYOUT2                 ( 0x025c )
#define REG_PIN_KEYIN0                  ( 0x0260 )
#define REG_PIN_KEYIN1                  ( 0x0264 )
#define REG_PIN_KEYIN2                  ( 0x0268 )
#define REG_PIN_SCL2                    ( 0x026c )
#define REG_PIN_SDA2                    ( 0x0270 )
#define REG_PIN_CLK_AUX0                ( 0x0274 )
#define REG_PIN_IIS1DI                  ( 0x0278 )
#define REG_PIN_IIS1DO                  ( 0x027c )
#define REG_PIN_IIS1CLK                 ( 0x0280 )
#define REG_PIN_IIS1LRCK                ( 0x0284 )
#define REG_PIN_TRACECLK                ( 0x0288 )
#define REG_PIN_TRACECTRL               ( 0x028c )
#define REG_PIN_TRACEDAT0               ( 0x0290 )
#define REG_PIN_TRACEDAT1               ( 0x0294 )
#define REG_PIN_TRACEDAT2               ( 0x0298 )
#define REG_PIN_TRACEDAT3               ( 0x029c )
#define REG_PIN_TRACEDAT4               ( 0x02a0 )
#define REG_PIN_TRACEDAT5               ( 0x02a4 )
#define REG_PIN_TRACEDAT6               ( 0x02a8 )
#define REG_PIN_TRACEDAT7               ( 0x02ac )
#define REG_PIN_EXTINT0                 ( 0x02b0 )
#define REG_PIN_EXTINT1                 ( 0x02b4 )
#define REG_PIN_SCL3                    ( 0x02b8 )
#define REG_PIN_SDA3                    ( 0x02bc )
#define REG_PIN_U1TXD                   ( 0x02c0 )
#define REG_PIN_U1RXD                   ( 0x02c4 )
#define REG_PIN_U2TXD                   ( 0x02c8 )
#define REG_PIN_U2RXD                   ( 0x02cc )
#define REG_PIN_U3TXD                   ( 0x02d0 )
#define REG_PIN_U3RXD                   ( 0x02d4 )
#define REG_PIN_U3CTS                   ( 0x02d8 )
#define REG_PIN_U3RTS                   ( 0x02dc )
#define REG_PIN_U4TXD                   ( 0x02e0 )
#define REG_PIN_U4RXD                   ( 0x02e4 )

/* bits definitions for register REG_PIN_XXX */
#define BITS_PIN_DS(_x_)                ( ((_x_) << 19) & (BIT_19|BIT_20|BIT_21|BIT_22) )
#define BIT_PIN_SLP_AP                  ( BIT_13 )
#define BIT_PIN_SLP_CP0                 ( BIT_14 )
#define BIT_PIN_SLP_CP1                 ( BIT_15 )
#define BIT_PIN_SLP_VCP0                ( BIT_16 )
#define BIT_PIN_SLP_VCP1                ( BIT_17 )
#define BITS_PIN_SLP(_x_)               ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15|BIT_16|BIT_17) )
#define BIT_PIN_WPU_SEL                 ( BIT_12 )
#define BIT_PIN_WPU                     ( BIT_7 )
#define BIT_PIN_WPD                     ( BIT_6 )
#define BITS_PIN_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
#define BIT_PIN_SLP_WPU                 ( BIT_3 )
#define BIT_PIN_SLP_WPD                 ( BIT_2 )
#define BIT_PIN_SLP_IE                  ( BIT_1 )
#define BIT_PIN_SLP_OE                  ( BIT_0 )

/* vars definitions for controller CTL_PIN */
#define BIT_PIN_NUL                     ( 0 )
#define BIT_PIN_SLP_NUL                 ( 0 )
#define BIT_PIN_SLP_Z                   ( 0 )
#define BIT_PIN_WPU_SEL                 ( BIT_12 )
#define BIT_PIN_WPUS                    ( BIT_12 )
#define BIT_PIN_NULL                    ( 0 )

/*here is the pinmap info of adie such as 2723*/
#define CTL_ANA_PIN_BASE			(ANA_PIN_BASE)

/* registers definitions for controller CTL_PIN */
#define REG_PIN_ANA_EXT_XTL_EN0			( 0x04 )
#define REG_PIN_ANA_PBINT			( 0x08 )
#define REG_PIN_ANA_PBINT2			( 0x0C )
#define REG_PIN_ANA_ADI_SCLK			( 0x10 )
#define REG_PIN_ANA_ADI_SYNC			( 0x14 )
#define REG_PIN_ANA_ADI_D			( 0x18 )
#define REG_PIN_ANA_AUD_DASYNC			( 0x1C )
#define REG_PIN_ANA_AUD_DAD0			( 0x20 )
#define REG_PIN_ANA_AUD_DAD1			( 0x24 )
#define REG_PIN_ANA_AUD_ADSYNC			( 0x28 )
#define REG_PIN_ANA_AUD_ADD0			( 0x2C )
#define REG_PIN_ANA_AUD_SCLK			( 0x30 )
#define REG_PIN_ANA_CLK_32K			( 0x34 )
#define REG_PIN_ANA_XTL_BUF_EN1			( 0x38 )
#define REG_PIN_ANA_XTL_BUF_EN0			( 0x3C )
#define REG_PIN_ANA_CHIP_SLEEP			( 0x40 )
#define REG_PIN_ANA_EXT_RST_B			( 0x44 )
#define REG_PIN_ANA_ANA_INT			( 0x48 )
#define REG_PIN_ANA_PTEST			( 0x4C )

/* bits definitions for register REG_PIN_XXX */
#define BITS_ANA_PIN_DS(_x_)                ( ((_x_) << 8) & (BIT_8|BIT_9) )
#define BIT_ANA_PIN_WPU                     ( BIT_7 )
#define BIT_ANA_PIN_WPD                     ( BIT_6 )
#define BITS_ANA_PIN_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
#define BIT_ANA_PIN_SLP_WPU                 ( BIT_3 )
#define BIT_ANA_PIN_SLP_WPD                 ( BIT_2 )
#define BIT_ANA_PIN_SLP_IE                  ( BIT_1 )
#define BIT_ANA_PIN_SLP_OE                  ( BIT_0 )

#endif //_PINMAP_H_

